Why AI Chiplets and Photonics Make Thermal Design Harder

Thermal design for AI systems is becoming a system-level problem. Stacked dies, high-bandwidth memory and photonics bring together components with different heat patterns and response times. A design that looks sound when each component is analyzed alone can behave differently once the parts share a package.

That makes early, combined modeling more valuable—and exposes gaps in the tools used to predict long-term reliability. In a discussion at the Design Automation Conference, engineers from Synopsys, Silvaco, Vinci, Keysight EDA and Siemens EDA described why transient heat, mechanical stress and aging need to be considered alongside electrical and optical performance.

L-R: Silvaco’s Berg; Synopsys’ Lin; Vinci’s Radhakrishnan; Keysight’s Mueth; Siemens’ Ferguson.

Photonics trades data movement for thermal control work

Photonics could help reduce data movement bottlenecks while using less energy, but the approach still faces practical limits. Chris Mueth of Keysight EDA said that building a large mesh switch requires many components and incurs high losses. Scaling such systems may require a modular architecture and a rethink of how the photonic components are arranged.

Heat sensitivity adds another design burden. Photonic structures need temperature stabilization, often using heaters that actively control their behavior. A large switch could require thousands of heaters, raising a difficult calibration problem: designers need to coordinate those control elements across the chip while maintaining the desired optical performance. Solving calibration alone would not address the losses, Mueth cautioned; the architecture must also scale efficiently.

Silicon photonics also behaves differently from digital logic under heat. Lang Lin of Synopsys compared it to an analog circuit: digital transistors switch, while photonic and analog devices can carry steady current. Current flowing through interconnects generates heat. In co-packaged optics, some of that heat is part of operating the electronic integrated circuit, but densely placed heaters can create local hot spots and interfere with nearby devices. Their placement and the resulting mechanical stress need to be part of the design.

Thermal effects also reach components that chip design traditionally treated as less sensitive. Mueth noted that engineers once focused thermal analysis on semiconductor devices and often paid less attention to passive components. Photonics changes that assumption: temperature can affect the passive optical structures as well.

Packaging creates interacting heat and stress

Co-packaged optics places electronic and photonic components close together, which can shorten connections but also couples their thermal behavior. Satish Radhakrishnan of Vinci said that the electronic integrated circuit driver may sit near or above the photonic integrated circuit. Heat from the driver can then affect the photonic structure, while the two components respond on different time scales.

A steady-state simulation can miss those effects. Heat takes time to travel through a package, so a later workload pulse may arrive while the warmth from an earlier one is still present. Even small temperature changes can shift a ring oscillator, Radhakrishnan said. Designers need to simulate the system in the transient domain to understand whether the optical and electronic parts will function reliably under changing workloads.

Temperature is only part of the picture. Moving components to manage heat can introduce new mechanical stresses, and those stresses may affect optical signals as much as, or more than, the temperature change itself. Chris Mueth and John Ferguson of Siemens EDA both emphasized that placement decisions can make performance worse if the combined thermal and mechanical effects aren’t understood.

Monitoring temperatures inside a photonic chip presents its own challenge. Mueth said calibration could use a sensing loop within the photonic integrated circuit, but adding one makes the design more complicated. The sensor must provide useful information without creating an excessive burden for calibration and control.

Warpage adds another physics problem

Heat can warp chips and alter the alignment of features. Jack Berg of Silvaco said photonic integrated circuits are more sensitive to thermal variation and warpage than electronic integrated circuits. A laser can also act as a heat source, creating a reliability concern within the package.

That sensitivity expands the simulation workload. Photonics design may require electrical, mechanical, thermal and optical models to work together. Berg said those models can make analysis substantially more involved than for electronic circuits alone. Thin dies add another trade-off: flattening warped components may affect their ability to dissipate heat.

Because these effects interact, checking each discipline in isolation can give an incomplete answer. A change that improves heat flow might increase stress; a mechanical adjustment might alter optical behavior. Designers need a way to evaluate those consequences across the system while the package and component layout are still being developed.

Transient modeling could turn power into a design variable

AI systems increasingly combine multiple dies because a single die may not provide the needed performance or bandwidth. Coordinating those components means deciding when they should run at peak power, rather than assuming every die will operate at full load continuously.

Radhakrishnan argued that transient analysis could help teams make more specific decisions about short-lived workloads. A brief peak may fit within a system’s thermal headroom, depending on how long it lasts and how often it recurs. The relevant question is not just how hot a component gets at peak power, but whether the package has time to shed heat before the next pulse.

This approach could let designers set workload-specific limits. For example, a system might tolerate a short inference burst at higher power if it occurs infrequently enough. The acceptable pattern depends on the end use and the cooling available in the data center. Modeling those patterns early can connect performance targets to the thermal constraints that the finished system must meet.

Chris Mueth said high-performance use cases should be modeled during architecture work, including their thermal, electrical and mechanical behavior. That gives teams more opportunity to adjust the design before implementation choices become difficult to change. John Ferguson described the cost of waiting: running each analysis repeatedly until the results settle can take substantial effort, and a calculated steady state may not reflect how the system will actually be used.

Multi-die design needs shared models

System-level analysis also depends on models that can move between companies. Lin described a workflow in which a high-bandwidth memory supplier provides a model to a system integrator, which combines it with models for the other components in a multi-die stack. The integrator then evaluates the assembled system’s thermal behavior.

Hierarchical models help manage that work by allowing component-level descriptions to be combined without rebuilding every part of the simulation from scratch. They also support division of responsibility: suppliers can describe their own components, while the integrator checks how those parts behave together. Lin said shared standards are needed so models from different vendors can be connected and used across the design process.

Those models could make thermal analysis more practical as systems grow in size, but they need to capture interactions that matter in real workloads. A model that describes a component accurately on its own may still miss the effects of neighboring dies, changing power demand or package stress.

Aging remains a tool gap

Heat also accelerates wear in data paths, including degradation associated with electromigration. Radhakrishnan said some teams are embedding thermal sensors in dies to monitor aging. Software can use sensor readings to identify changes and throttle parts of a chip when needed. Sensor placement matters: designers must determine whether the measurements reflect the regions that are most likely to degrade.

Long service life makes the question more pressing in applications such as automotive, where chips may need to operate for 10 to 15 years. Ambient temperature also changes the aging picture. Berg pointed to the Arrhenius equation as a rule of thumb for temperature-dependent reliability and noted that hotter conditions can sharply reduce expected lifetime.

Yet monitoring wear and predicting it during design are different tasks. Lin said tools for accurately predicting thermally induced aging are lacking. Sensors can reveal degradation as it occurs, but designers still need methods that connect thermal conditions to aging forecasts and design choices. Radhakrishnan described the resulting balance as a risk of under-design or over-design, with the ideal approach adapting to conditions over time.

The practical takeaway is that thermal analysis needs to start with architecture and continue through the full package, including optical, mechanical and aging effects. Transient models and shared component data could help teams make better use of short power bursts, but reliable aging prediction remains an open need.

Read part one of the discussion:
Scaling Thermal Analysis From Transistors To Data Centers
Rising power density and chiplet complexity drive thermal considerations earlier in the design process.

Related:
Photonics Fundamentals For Electronics Engineers: eBook

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