Autonomous Chip Design Is Advancing, but Full Automation Remains Ahead

AI tools are taking on larger parts of chip development, but the path to a fully autonomous design flow is still incomplete. Synopsys CEO Sassine Ghazi says the company’s agents can already translate some customer specifications into verified RTL, the starting point for chip design. Extending that autonomy through physical implementation, verification and final sign-off remains a goal, not a capability he says is available today.

That distinction matters as chip buyers try to match hardware development to AI workloads that change on a much shorter cycle. System companies want to define and customize silicon faster, while advanced packages and physical products make it harder to optimize a chip in isolation. The technical shift is therefore broader than automating individual design tasks: it calls for coordinating software, workloads, silicon architecture and the physics of the finished product.

Ghazi discussed these changes in a live keynote interview with Semiconductor Engineering at SEMICON West. His account points to a design process where AI agents can handle more execution, but engineers still set the goals, make architectural choices and judge whether a result is ready to manufacture.

From design assistance to orchestrated agents

AI’s role in electronic design automation has grown over several stages. Ghazi said Synopsys introduced reinforcement learning into some technologies and tools around 2016. Those systems helped engineers search through large sets of design parameters and optimize toward a chosen result. In that model, AI supported a human who remained responsible for directing the work.

The newer approach uses task-specific agents. Ghazi said Synopsys has more than 40, each equipped with knowledge of particular tools and the capabilities needed to perform a defined task. Rather than asking one general-purpose model to complete every step, an orchestrating model can call on specialized agents as the work progresses.

The change he attributes to recent advances is the ability to reason across longer sequences of work. An engineer can specify an outcome, and the model can plan actions that involve multiple agents. That is a meaningful change from an assistant that responds to a prompt or generates a discrete artifact: the system is being asked to coordinate a workflow toward a goal.

Still, the tool and the agent serve different purposes. Ghazi described models as useful for reasoning and exploring options, while tools remain necessary to generate and validate designs. Exploring alternatives is only part of the job. Engineers must ultimately choose an implementation that balances targets such as performance, power and cost, then establish that it works.

That makes the agent’s expertise closely tied to the tools it operates. Ghazi framed the question for Synopsys as whether its core intellectual property lies in the design tools, the agents that know how to use them, or both. The interview does not resolve that question, but it suggests that useful automation depends on joining model reasoning to domain-specific design and validation capabilities.

Autonomous RTL is a milestone, not a finished flow

Today’s most concrete example in Ghazi’s account is the conversion of a system company’s specification into verified RTL. A customer can provide a specification to Synopsys Autonomous Agent, which then produces RTL and checks it. Ghazi said this stage once took many engineers months of work, including writing and verifying the RTL and confirming that it could be implemented physically and manufactured.

That capability moves a significant handoff earlier in the process. System companies define products and workloads; those needs have to be translated into an electronic specification that chip designers can implement. Automating the step to verified RTL could reduce the manual effort between those requirements and a workable starting design.

But verified RTL is not a manufactured chip. Ghazi said the technology has not yet expanded through physical implementation, physical verification and chip sign-off. He expects greater autonomy in those stages, while explicitly saying that end-to-end automation is not here today.

Human engineers remain part of the process in his account. They define the architecture, guide the work and perform the final check before manufacturing. That division may change as agents gain more responsibility, but the current evidence he describes supports a narrower claim: autonomy is being applied to defined parts of the workflow, with human judgment still shaping what is built and whether it is ready.

There is also a capacity argument. Ghazi said demand is growing for companies to define and specialize their own silicon, while the industry lacks enough engineers to architect chips and carry specifications toward a finished result. Automation could let engineering teams handle more work and more tailored designs. Whether it delivers that benefit will depend on how reliably agents can manage tasks beyond RTL and how much oversight those tasks require.

Customization depends on the workload

The push for custom silicon is tied to the limits of general-purpose components. Ghazi distinguished classic EDA tools from interface IP, which connects chips to one another and links a chip to the larger system. For a hyperscaler designing around a particular workload, a general interface may leave performance or area targets unmet. Customizing that IP can help fit the design to the intended use.

Workload context is becoming more important as AI models and the demands placed on them change. Ghazi said models can change every three to four months, while chips may take two to three years to update. He also described semiconductor customers trying to cut development cycles from 18, 16 and 14 months toward a year, and system companies asking whether AI could bring the path from specification to tape-out below a year or even nine months.

That pressure helps explain why system companies want more control over silicon development. The semiconductor industry already tunes chips for specific workloads, Ghazi said, but the pace of change creates a mismatch between evolving software and longer hardware cycles. Companies want to define a workload, specify silicon around it and get that silicon into use sooner.

Programmable chips and chiplets could offer room to adapt, but Ghazi said system companies are not yet adopting that approach as widely as the push for faster, workload-specific design. He described custom silicon as having a relatively short life in some applications: around two to three years, rather than multiple generations of a model. For those buyers, rapid delivery may matter more than designing a chip to serve a long succession of workloads.

The practical challenge is to shorten the engineering cycle without losing the ability to validate the result. A shorter schedule has limited value if important workload behavior or physical effects are missed. That is why Ghazi’s account connects agent orchestration to co-design across the stack: the specification, architecture, implementation and actual workload all need to inform one another.

Physical AI expands the design problem

As AI moves into vehicles, robots and other physical products, the target for optimization expands beyond the chip. Ghazi described a software-defined vehicle as part of a longer shift in the automotive industry, which he said has been moving in that direction for seven to 10 years. An autonomous product must be designed around its electronics and physical structure, as well as the environment in which it operates.

That can bring together silicon design, mechanical engineering, structural analysis, fluid behavior and environmental modeling. The aim is to understand how the parts interact before committing to a product. A design that works as an electronic model may still face physical constraints in its complete system, and engineers need a way to assess those interactions as they make choices.

Ghazi said Synopsys works from silicon to system through its acquisition of Ansys and its multiphysics capabilities. For a chip, car or robot, the design question includes whether the product is overbuilt and whether it can meet its needs without unnecessary material or performance margin. Modeling multiple physical effects early can inform those decisions and support sign-off before manufacturing.

The word “system” also changes meaning as engineers move between levels of abstraction. An advanced package can be treated as a system on its own. At the level of a rack or data center, that package becomes one component among many. Each level brings interactions that may not be visible when considering a single chip or subsystem alone.

That nested view helps explain why advanced packaging creates more than an electronics problem. A 3D integrated circuit combines multiple chips in a package, and Ghazi said such designs are already present in data centers. The challenge he highlighted lies in physical and mechanical behavior under demanding workloads. Heat inside the package can cause chiplets to warp or crack.

Those effects need attention while teams are choosing the architecture and workload, rather than after the hardware is built. A workload can create short, intense periods of activity, and the resulting heat and mechanical stress may expose a condition that designers did not account for. Ghazi said the industry is working to address those issues during design, with physics simulation brought into the process early.

In a multi-die system, software behavior affects the package, and the package’s physical limits affect the software and architecture decisions. The design task therefore runs from workload and software through chip and package implementation, with physics considered along the way. A corner case that escapes this analysis can lead to an overheating system that fails in use.

Digital twins are useful in parts, but still incomplete

Digital twins have supported chip development for years, according to Ghazi. Synopsys made two acquisitions around 15 or 17 years ago focused on virtualizing chips. A virtual chip model lets a customer begin software development before the physical chip exists, and can help compare which chip model fits a system.

Digital models are also being used in parts of vehicle engineering. Ghazi said some customers can model a vehicle’s electronics and use simulation to assess crash behavior, materials, structure and physics without relying solely on physical prototypes and testing. These are useful examples, but they cover separate engineering areas rather than every aspect of a complete product.

He said a widely used twin that joins electronics, physical behavior and the operating environment is not yet generally available. That is the larger target: a virtual representation that lets teams assess how an intelligent system behaves across its connected components and conditions. Ghazi argued that building sophisticated future systems without such models could take a very long time and cost far more, though the interview does not specify when a full version might become practical.

Digital twins can also support a more iterative design process. Ghazi described the usual approach as starting from an earlier design and architecture, then modifying them for the next product. A fully digital process can be harder for established engineering companies to adopt because they must maintain current commitments while changing how their teams work.

He pointed to newer companies in China working on robotics and electric vehicles as an example of a different starting point. In his description, some companies founded two or three years ago began with digital design. After their silicon was fabricated, they put it on a board and into the finished system, with software running within weeks. The important distinction is the whole workflow: digital design can link chip development and product iteration more tightly when a company builds its process around that approach from the outset.

Ghazi contrasted that pace with traditional automakers, which he said typically create a new vehicle platform every four or six years. The companies in his example update electronics and the broader vehicle on a cycle of nine months to a year. That approach requires significant computing resources, but Ghazi argued it can produce a more differentiated product and support a faster engineering rhythm.

Designing systems as individual components that can be validated together may also provide flexibility. Ghazi said that approach can give teams options based on cost, supply chain and other factors. The point is not that a particular chip must remain in a vehicle for a fixed period; it is that modular design and system-level validation can help teams weigh alternatives as product needs change.

Speed adds complexity to engineering teams

Ghazi described the pace of change as his main concern. Companies have to keep delivering what customers expect while also reshaping engineering workflows to bring intelligence, physical analysis and product-specific design together. A new process can be easy to describe in a presentation and much harder to put into practice when the same teams are responsible for existing products and future ones.

That transition affects investment as well as staffing. EDA companies have long spent a high share of revenue on research and development, Ghazi said. AI has not yet reduced that pressure in his view. Synopsys’ investment is continuing to increase, as the company works to keep pace with greater design complexity and new ways of building chips.

The near-term test is whether AI can make more of the workflow faster while preserving the checks needed to manufacture dependable silicon. Verified RTL is a useful step, but physical implementation, package behavior and system-level validation remain substantial parts of the job. As AI workloads keep changing, the value of autonomy will depend on how well these pieces can be coordinated, and how quickly engineers can adopt a new process without losing control of the final design.

For now, autonomous chip design is best understood as a growing set of capabilities rather than a hands-off production line. Agents can take on more defined tasks, and system companies are pressing for shorter paths from specification to silicon. The next evidence to watch is whether that autonomy can extend into physical design and sign-off, where workload, packaging and multiphysics constraints meet.

The interview appeared in Semiconductor Engineering’s discussion of autonomous chip design. The publication is Semiconductor Engineering.