Semiconductor Scaling Shifts to Packaging, Photonics and AI

The semiconductor industry has already passed the $1 trillion annual revenue mark it once expected to reach by 2030. At SEMICON West 2026 in San Francisco, the question was what comes next: how to build increasingly complex systems quickly, reliably and affordably enough to meet demand.

SEMI President and CEO Ajit Manocha forecast a market exceeding $2 trillion by 2030 and potentially $3 trillion by 2035. The association also projected $149 billion in spending on 300mm fab equipment this year, rising to $227 billion by 2029. Construction is set to begin on 20 new 300mm fabs or production lines in 2026.

AI infrastructure accounts for much of the expansion, while electrification, autonomous vehicles, robotics and industrial automation add demand of their own. The harder change is that the systems built around chips are becoming more complicated. Transistor scaling still matters, but it no longer describes the full job. Performance increasingly depends on coordinating compute, memory, power, cooling, packaging, optics and manufacturing.

That coordination is changing how engineering teams approach design. Synopsys president and CEO Sassine Ghazi described a need to “re-engineer engineering” through co-design across materials, process technology, architecture, design and software. The model itself can define the workload, he said, so optimization has to account for the whole stack.

Performance depends on the whole package

At the show, discussions of transistor scaling, high-bandwidth memory, optical links and cooling repeatedly led to the same issue: gains in one area can expose limits in another. More compute raises demands on memory bandwidth and power delivery. Moving memory nearer to processors can reduce data movement, but it also concentrates heat. Splitting a large die into smaller pieces can improve yield and let each function use a suitable process node, yet it adds interfaces that must be connected, powered, cooled and tested.

Intel Foundry vice president of semiconductor R&D Lalitha Immaneni said packaging has become “the place where system innovation begins.” Memory placement, data movement, power and thermal management are no longer details to address after the chip architecture is set. They shape that architecture from the start.

“The challenge is not to co-optimize one component,” Immaneni said. “It is to co-optimize across the system from end to end between silicon, packaging, and platform.” Marvell vice president of advanced packaging Nitin Deshpande made a similar case at imec’s pre-show ITF USA program, describing a package as a system that brings compute, memory, interconnects, power and cooling together.

Integration alone doesn’t make a viable product. Complex packages still need acceptable yield, reliability and cost at high production volumes, with a supply chain able to provide parts on time. Deshpande cautioned that a promising concept has little commercial value if manufacturers cannot produce it reliably and at scale.

Imec CEO Patrick Vandenameele drew a distinction between adding hardware and conventional semiconductor scaling. Data centers can grow by adding accelerators and racks, he said, but that looks more like multiplication than the scaling semiconductor engineers traditionally mean. The distinction captures the industry’s new challenge: keeping up with demand now depends as much on combining technologies into working systems as on making individual components smaller or faster.

Fig. 2: Redefining a system. Source: SEMI

AI moves from assistance to delegated work

AI is becoming part of the industry’s engineering process as well as a major source of chip demand. Machine learning has already been used in design, process control and defect classification. Generative AI made it easier to interact with complex tools and data using natural language. The newer step is agentic AI: a system receives an objective and can call tools, models or other agents to work toward it.

Ghazi described the progression as moving from an assistant or copilot, through generative capabilities, to “long-horizon autonomous agents” that receive an outcome rather than a prompt. That shift matters because engineers are trying to search design and process spaces too large for manual exploration.

Lam Research chief AI officer and corporate vice president of Semiverse Solutions David Fried said the parameter space engineers face has become intractable. A current Lam etcher can have a potential recipe space on the order of 10²³ possibilities, he said. AI can help explore large, interconnected sets of parameters and sensitivities that no engineer could review one by one.

Finding a useful setting is only part of the job. A system that flags an unusual process signature is making a different kind of contribution from one that changes a recipe. Predicting equipment degradation doesn’t automatically mean an agent should stop production. The practical question is where companies place the boundary between recommendation and action.

Ghazi said Synopsys has engagements in which autonomous agents can take a customer specification through verified RTL, a task that traditionally involved multiple engineers and months of work. People still define the architecture and approve it before manufacturing. Even so, the example shows that AI is already being given responsibility for substantial engineering work.

Manufacturing raises further questions: which decisions can an agent make on its own, how are its actions constrained by physics-based models, and what evidence is needed before a decision affects production? AI use in design and manufacturing is already under way. The next measure of progress will be how much authority engineers are prepared to delegate and how they establish confidence in the result.

Fig. 3: What comes next is an evolving topic of great interest to a lot of people. Source: SEMI

Packaging needs evidence at every step

Advanced packaging has moved past proving that heterogeneous integration is possible. Manufacturers now need to assemble different components repeatedly and economically, while detecting defects before a costly build progresses too far. That puts new weight on the idea of “known good” parts and subassemblies.

Intel Fellow and director of substrate and advanced packaging pathfinding Ravi Mahajan said Intel sorts even passive silicon bridges, which contain metal lines, so that known-good bridges go into packages. The finished package must also be checked. But he described “known good” as a practical goal rather than a guarantee: manufacturers can add test features and gather enough information to reduce uncertainty before the next step.

ASE executive vice president Yin Chang described a similar approach in fan-out assembly flows, where interconnect structures can be tested before active silicon is attached. “Everything we do, every layer, we have the ability to confirm that it is good before we put on the most expensive part,” Chang said.

The sums involved make that sequence consequential. Chang said some silicon and HBM combinations can represent as much as $30,000 in value. ASE uses automated optical inspection (AOI) and X-ray extensively, with AI helping identify subtle differences in assemblies that may contain as many as half a million joints. The aim, Chang said, is to reduce unknowns in a process where scrapping an assembly is already too expensive.

Inspection has limits, because assembly changes the object being inspected. Bonding creates new interfaces, while heat, pressure and material interactions can alter the assembly. A defect may not become visible until a later process step. Manufacturers therefore have to decide how much uncertainty they can carry forward as each additional stage adds value.

Test and inspection follow the device

Optics adds another complication to manufacturing test. Digital tests can often compare a response with an expected result. Optical devices may produce a range of acceptable responses, and those results need to be correlated with defects. Co-packaged optics also changes the physical form of the assembly, affecting how it can be handled and probed.

Amkor senior director of manufacturing test technology Vineet Pancholi said customers want outsourced assembly and test providers to perform electrical and optical probing from both sides of a package efficiently. Its physical dimensions, weight and component density are changing, he said, while customers still expect efficient production testing.

The broad sequence of probe, burn-in, final test and system-level test remains in place. But adding optical test content is expected to increase test times in the short term, Pancholi said. Those times could fall as fabrication and assembly processes mature and manufacturers learn which defects matter.

Diagnosing a problem also increasingly depends on preserving information from earlier steps. Microtronic CEO Reiner Fenske said historical wafer images can help bracket where an issue arose, even when the precise process level isn’t immediately clear. As more layers are added, a defect from an earlier step can become difficult or impossible to inspect directly.

Microtronic retains wafer images so manufacturers can retrieve a lot’s process record later. Fenske said customers value that history enough for throughput to become a secondary concern. That record can be useful months after production, when engineers need to compare a defect with earlier images and process data.

The practical challenge is connecting that information to the right device and the right point in its manufacturing history. Wafer results, inspection images, assembly records and test insertions can inform later tests or help identify process drift. But tracing a die from its original wafer coordinates through reconstituted wafers, panels and multi-die packages is increasingly difficult.

Test is becoming a continuing evidence trail rather than a single pass-or-fail checkpoint. AI can search that history for patterns, but its conclusions are only useful when the underlying data remains tied to the right device, process step and physical context.

Optics brings manufacturing constraints closer to compute

As bandwidth and distance rise, electrical interconnects face growing pressure from power consumption and signal integrity. That has driven optics from pluggable modules toward near-package and co-packaged designs. Bringing optical components closer to compute can help address interconnect constraints, but it also makes precision assembly and manufacturing yield part of the system problem.

Intel Foundry senior technologist Huan Ma said precision bonding needs to control all six degrees of freedom while also meeting semiconductor manufacturing requirements for throughput, automation and standardized material handling. Optical components must remain aligned through assembly, reflow and reliability testing. Manufacturers also need metrology that measures features tied to optical yield, including geometry, angles and position, along with their effects on insertion loss and coupling efficiency.

“Co-packaged optics will not scale just because the optics work,” Ma said. “It will only scale when we industrialize the optics through advanced packaging.” That requires manufacturers to measure alignment across many dies without letting inspection time become a bottleneck.

Companies at the show described different parts of that work. EV Group pointed to the metrology and throughput demands of measuring multiple alignment points across hundreds of dies in die-to-wafer integration. Lam Research discussed waveguide fabrication, modulator materials and fiber coupling. Advantest identified high-volume test as another constraint, with electro-optical probing and optical connectors adding requirements that electrical testing doesn’t have.

Assembly can also undo what testing established earlier. Alignment, bonding, thermal steps and fiber attachment can change an optical path that met specifications before integration. Mahajan said the key question after checking the photonic integrated circuit and electronic integrated circuit is whether alignment can be maintained. Because photonics assembly steps may not be recoverable or reworkable, Intel has focused on identifying the points that limit yield.

Mahajan said he sees no inherent barrier to these processes, pointing to improvements in fiber attachment through repeated manufacturing experience. His assessment is that execution and process learning will determine how quickly co-packaged optics advances from working designs to production volumes. Alignment, inspection, test and assembly repeatability are the measures to watch.

Engineering models have to connect

The common thread across packaging, photonics, test and AI is that engineering boundaries no longer match the physical system. A packaging choice affects heat. Memory placement affects power. Photonics affects assembly and test. Inspection produces data that AI may use to guide manufacturing.

Immaneni described the shift as moving from design-technology co-optimization toward system-technology co-optimization, with silicon, packaging and platform considered together. A technology that performs well in isolation may still fail as a customer product if manufacturers can’t produce it repeatedly, quickly and with consistent quality.

Digital twins can help connect decisions across electrical, thermal, mechanical and manufacturing models, but only when those models are sufficiently linked to assess consequences across domains. Ghazi also argued that workload behavior belongs in that picture: the model running on hardware influences its power use and thermal conditions. As AI extends into robots, vehicles and other physical systems, sensors, real-time behavior and safety requirements add further constraints.

Fig. 4: View from the show floor. Source: SEMI

What to watch next

The next SEMICON West is scheduled for March 30 through April 1, 2027, at the Phoenix Convention Center. SEMI has signed a three-year agreement for the event in Phoenix, beginning a new spring schedule. With about five months between the 2026 and 2027 shows, several signs of progress should come into view quickly.

For agentic AI, the useful measure will be which engineering and manufacturing decisions companies let agents make, and what constraints they put around those actions. For heterogeneous integration, the test will be whether inspection and metrology can build confidence before expensive components are committed to assembly. For co-packaged optics, the question is whether precision alignment, optical test and manufacturing throughput become repeatable at production volumes.

Other areas will add pressure to the same system-level effort. High-NA EUV is moving toward production, power delivery is moving deeper into packages, and materials suppliers are being asked to account for interface and process interactions that conventional specifications may not capture.

SEMICON West 2023 focused on a path to $1 trillion by 2030. The industry crossed that milestone years early, and its next challenge is broader than increasing transistor density or making more chips. Progress will depend on integrating complex systems and producing them with enough yield, reliability and cost control to keep pace with demand.

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